1. Field of the Invention
The present invention relates to a charge pump circuit, and more particularly to a charge pump circuit which dissipates small power.
2. Related Art
An example of a conventional charge pump circuit is shown in FIG. 7. The charge pump circuit shown in FIG. 7 includes: a booster clock driver 700 for driving a booster capacitor C1 by inputting a clock signal OSC shown in FIGS. 8A and 8B; a booster 701 constituted by an N-channel MOS transistor N1 for supplying a power supply voltage Vdd to the booster capacitor C1 and an N-channel MOS transistor N2 for supplying a booster voltage to a capacitor C2 for holding the booster voltage; and a limiter 703 for stabilizing the booster voltage output from the booster 701.
An operation of the charge pump circuit shown in FIG. 7 will now be described with reference to FIGS. 8A and 8B. FIG. 8A shows a waveform of a clock signal OSC and FIG. 8B shows a waveform of an output voltage Vout.
When the clock signal OSC shown in FIG. 8A is at the power supply voltage Vdd, the N-channel MOS transistor N3 is turned on and the P-channel MOS transistor P3 is turned off. Accordingly, a ground potential is supplied to a signal line E3. The booster capacitor C1 is charged by the power supply voltage Vdd through the N-channel MOS transistor N1. The potential V1 of the signal line E1 is expressed by equation (1) when a threshold value of the N-channel MOS transistor N1 assumed to be Vtn1. EQU V1=Vdd-Vtn1 (1)
When the clock signal OSC is changed to the ground potential, the N-channel MOS transistor N3 is turned off, and the P-channel MOS transistor P3 is turned on. Accordingly, the signal line E3 is charged to the power supply potential Vdd. A potential V1 of a signal line E1 is boosted by capacitive coupling and expressed by equation (2). EQU V1=2.multidot.Vdd-Vtn1 (2)
Since the potential V1 exceeds a gate potential of the N-channel MOS transistor N1, the N-channel MOS transistor N1 is turned off. Accordingly, the charges charged by the signal line E1 are seldom discharged to the power supply Vdd side. Furthermore, since the potential of the signal line E1 is applied to a gate of the N-channel MOS transistor N2, the N-channel MOS transistor N2 is turned on and the capacitor C2 is charged. If the limiter 703 constituted by the P-channel MOS transistors P1 and P2 is absent, the potential Vout of the signal line E2 is boosted as shown by the dotted line in FIG. 8B and reaches a value expressed by the equation (3) when a threshold value of the MOS transistor N2 is assumed to be Vtn2. EQU VOUT=2.multidot.Vdd-Vtn1-Vtn2 (3)
However, this voltage VOUT is stabilized by the limiter 703 (limited by the threshold values Vtp1, Vtp2 of the MOS transistors P1 and P2 and the power supply voltage), changed as shown by the solid line in FIG. 8B, and reaches a value expressed by the equation (4). EQU VOUT=Vdd+Vtp1+Vtp2 (4)
The potential difference V12 between the right side of the equation (3) and the right side of the equation (4) is expressed by equation (5). EQU V12=Vdd-Vtn1-Vtn2-Vtp1Vtp2 (5)
The limiter 703 serves as a constant current source and current i flows into the limiter 703.
A power W4 dissipated by the limiter 703 is expressed by equation (6). EQU W4-i.multidot.(Vdd-(Vtn1+Vtn2)-(Vtp1+Vtp2)) (6)
According to a conventional charge pump circuit, as shown in equation (6), the more the power supply voltage is high, the more the difference between the booster voltage expressed by the equation (3) and the limited potential expressed by the equation (4) becomes large, resulting in increased power dissipation.